1. Field of the Invention
The present invention relates to signal detection circuits for detecting whether there are signals having the same logic in a plurality of arranged signal lines, and more particularly pertains to a signal detection circuit suitable for multi-hit detection in a content addressable memory.
2. Description of the Related Art
Hitherto, a signal detection circuit built in a content addressable memory (hereinbelow, abbreviated and referred to a CAM) has been used for multi-hit detection. Data stored in CAM words is searched using a search key data. A signal indicating that the stored data has matched the search key data is called a hit flag. The signal detection circuit detects whether there are hit flags in a plurality of word match lines arranged in the CAM (the presence of the hit flags in the match lines is called multi-hit). A signal detection circuit comprising AND gates is known as one of the above-mentioned signal detection circuits. In this signal detection circuit, sense outputs of two arbitrary match lines are supplied to one of a plurality of 2-input AND gates to determine the logic between the sense outputs, and the outputs of the plurality of 2-input AND gates are input to at least one OR gate, thus detecting the presence or absence of multi-hit. The number of combinations of AND gates in the signal detection circuit is determined by the number of match lines. In order to detect multi-hit among several hundreds of match lines, the scale of the circuit must be enormously increased. To overcome such a disadvantage, Japanese Patent Application Publication No. 6-231588 (corresponding to U.S. Pat. Nos. 5,726,942 and 5,999,434) proposes a technique of detecting multi-hit using a dynamic circuit.
FIG. 8 shows a signal detection circuit disclosed in this prior art.
Referring to FIG. 8, a signal detection circuit 100 is built in a CAM. This circuit 100 includes a sense amplifier 110. The sense amplifier 110 comprises PMOS transistors 111, 112, 113, and 114, NMOS transistors 115, 116, 117, and 118, and inverters 119_1 and 119_2.
This circuit 100 further includes a precharge circuit 120, a reference circuit 130, and detection circuits 140. The precharge circuit 120 comprises PMOS transistors 121, 122, and 123, of which the respective gates are connected commonly to each other. The reference circuit 130 comprises an NMOS transistor 131, of which the gate is connected to ground, and an NMOS transistor 132, of which the gate is connected to a power supply. Each detection circuit 140 comprises an NMOS transistor 141 in which a hit flag signal HF is input to the gate, and an NMOS transistor 142, of which the gate is connected to ground. The precharge circuit 120, the reference circuit 130, and the detection circuits 140 are connected to the sense amplifier 110 through a sense line 151 and a reference line 152. The size (gate width w) of each of the NMOS transistors 131 and 132 in the reference circuit 130 is substantially 1.5 times as large as that of each of the NMOS transistors 141 and 142 in the detection circuit 140.
The signal detection circuit 100 further includes inverters 161, 162, 163, 164, and 166, a NAND gate 165, an NMOS transistor 167, and a wired OR line 168.
In the signal detection circuit 100 with the above-mentioned structure, in order to search data stored in CAM words to detect multi-hit, a control signal CNT is first set to a level “H” (high). Consequently, the PMOS transistors 121, 122, and 123 of the precharge circuit 120 are turned on, thus precharging the sense line 151 and the reference line 152 and equalizing the potentials of these lines with each other to a power supply potential. The control signal CNT at the level “H” is changed to a level “L” (low) through the inverter 161. The control signal CNT at the level “L” is supplied to the respective gates of the PMOS transistors 111 and 114 in the sense amplifier 110. Thus, the PMOS transistors 111 and 114 are turned on. Consequently, a node between the PMOS transistor 111 and the NMOS transistor 116 and a node between the PMOS transistor 114 and the NMOS transistor 117 are also held to the power supply potential.
A search is then performed. As the result of the search, if the CAM word is not hit, a hit flag signal HF at the level “L” is input to the NMOS transistor 141 of the detection circuit 140. Therefore, both of the NMOS transistors 141 and 142 are in the OFF state.
Simultaneously with the input of the hit flag signal HF to the detection circuit 140, the control signal CNT is changed from the level “H” to the level “L”. After that, a node between the NMOS transistors 131 and 132 in the reference circuit 130 goes to the level “L”. Since the gate of the NMOS transistor 132 is connected to the power supply, the NMOS transistor 132 is turned on, thus discharging the reference line 152.
As the result of the search, if the search key data has hit only data stored in one CAM word, a hit flag signal HF at the level “H” is input to the NMOS transistor 141 of either of the detection circuits 140. Consequently, the NMOS transistor 141 is turned on, thus discharging the sense line 151. Since the size (gate width w) of the NMOS transistor 132 is substantially 1.5 times as large as that of the NMOS transistor 141, the discharge rate of the reference line 152 is higher than that of the sense line 151.
In this instance, when search key data hits data stored in two CAM words, the NMOS transistors 141 of the two detection circuits 140 are turned on. Since the two NMOS transistors 141 are in the ON state, the discharge rate of the sense line 151 is higher than that of the reference line 152. In other words, the potential gradient during the discharge of the sense line 151 and that during the discharge of the reference line 152 vary in some cases, namely, when there is no hit, when one hit is detected, and when two hits are detected. Therefore, a difference between the potentials is amplified by the sense amplifier 110 and the amplified output is then generated through the NAND gate 165, the inverter 166, and the NMOS transistor 167. In the case of two hits or more, an output at the level “H” is generated from the sense amplifier 110, thus finally turning the NMOS transistor 167 on. Consequently, the potential of the wired OR line 168 indicating the presence of multi-hit goes to the level “L”. As mentioned above, the signal detection circuit 100 detects the presence or absence of multi-hit.
In recent years, the number of entries (the number of words) in the CAM is becoming increasingly larger. In the conventional signal detection circuit 100 shown in FIG. 8, as the number of entries increases, the length of the sense line and that of the reference line are increased and the number of discharging transistors connected to the sense line is also increased. Disadvantageously, a malfunction may occur due to the following causes.
For the first cause, as the load capacity of the sense line and that of the reference line increase, the discharge rate of the sense line and that of the reference line deteriorate. Consequently, a difference between the potentials of the sense and reference lines at the sensing point of the sense amplifier relatively decreases.
For the second cause, since the respective lengths of the sense line and the reference line increase, the lines are susceptible to ambient noises. Particularly, in the CAM, since current consumption is large and a peak current is high in the search operation, the power supply potential and a ground potential vary excessively. In recent years, since a power supply voltage is becoming lower, the CAM is susceptible to noises caused by the variations.
To avoid malfunctions caused by the first and second causes, the following signal detection circuit is proposed. In the signal detection circuit, the length of each of the sense line and the reference line is reduced and the number of discharging transistors connected to the sense line is also reduced. In other words, a section to detect multi-hit is divided into small unit groups. However, when the respective lengths of the sense line and the reference line are short, the respective discharge rates becomes higher, resulting in a small difference between the potential of the sense line and that of the reference line. Accordingly, it is difficult to control the signal detection circuit.
Since the detection section is divided into small unit groups, the number of sense amplifiers is increased, and the area of the signal detection circuit also increases in the CAM. This results in an increase in the area of a semiconductor chip including the CAM. Further, since the section is divided into small unit groups, layout design is complicated.
Furthermore, recent finer semiconductor processing results in an increase in the sheet resistance of a metal film and an increase in the resistance of a via hole. Accordingly, the circuit is extremely sensitive to the symmetry of layout.